夏宇聞

[NT 60487] Overview

[NT 60478] Works:	2 [NT 60520] works in 1 [NT 60521] publications in 1 [NT 60522] languages

[NT 60480] Titles

Verilog HDL数字设计与综合 [NT 59711] by: Palnitkar,, Samir; 刁嵐松; 夏宇聞; 巴尼卡 ((Palnitkar, Samir)); 胡燕祥 ([NT 1579] Language materials, printed) , [譯]

[NT 60479] Subjects

電腦 VHDL語言